1. Field of the Invention
This invention relates to delay compensator circuits that compensate for propagation delay variation caused by varying circuit parameters such as supply voltage, temperature, and process. This invention also relates to delay monitor circuits.
2. Description of the Relevant Art
Several parameters influence the propagation delay through electrical circuits. Variations in supply voltage, generally termed as VCC or VDD, with respect to a reference potential, generally termed as GND or VSS, cause corresponding variations in the delay through semiconductor circuits. In particular, the delay of CMOS circuits decreases with an increase in supply-to-reference potential.
Variations in temperature also affect delays through semiconductor circuits. Delays in CMOS circuits decrease with a decrease in temperature, usually quantified in terms of junction temperature.
In addition, semiconductor circuits also suffer from variations in the accuracy of the various steps in fabrication. These variations in fabrication are often referred to as process variations. Process variations could increase or decrease the delay through the circuits. These and other variations may apply similarly to circuits other than silicon circuits.
As a result of these varying conditions, manufacturers guarantee the operation of their devices over temperature and voltage ranges. ASIC manufacturers also provide to the customer or designer the variations in circuit delays that may be expected as a result of process, temperature and voltage variations. A CMOS circuit has the least delay when the supply voltage is the highest, the temperature is the lowest and process is "best", as specified by the manufacturer. "Best process" refers to the case when the circuit has the least propagation delays as a result of variations due to manufacturing inaccuracies. This combination of parameters is termed as "best case conditions", while lowest voltage, highest temperature and "worst" process is termed as "worst case conditions". The typical case is also generally quantified in terms of "typical" temperature, voltage and process conditions. The typical case indicates the most common temperature and voltage operating conditions as well as process.
As a result, there is a wide variation between the extremes "best case conditions" and "worst case conditions". Designers try to design circuits to be functional over this range. However, it is often difficult to achieve this goal if circuit requirements are aggressive. It is often necessary to provide a means to compensate circuit delays with changes in parameters such as temperature, voltage and process. A classical example where such compensation may be required is a circuit whose output has an output delay time and output hold time requirement from some reference. The output delay time of the signal is governed by the "worst case" or the slowest of the longest path, while the output hold of the signal is governed by the "best case" or fastest of the shortest path. A problem immediately arises if the requirements on the circuit are such that the ratio of the output delay time to the hold time is less than the "worst case" to "best case" variation. In this case, if the circuit is designed to meet the output delay time requirement, the circuit fails the output hold time requirement. Conversely, if the circuit is designed to meet the output hold time requirement, the output delay time requirement cannot be met.
Conventional methods for compensation include solutions from careful delay balancing of all related paths and circuit design of custom non-time base circuits that monitor process, temperature and voltage variations. Custom circuits that monitor such variations use circuit design techniques that enable a latch to hold the output for the required time after the reference. These circuits are carefully crafted to achieve this "process tracking" property and usually rely heavily on the fabrication process. Once fabricated correctly, these circuits track with changes in temperature, voltage and process.
Another technique has been detailed in U.S. Pat. No. 4,737,670, titled "Delay Control Circuit". This technique involves the use of a ring oscillator having a frequency that is inversely proportional to the propagation delays of the elements to calibrate the process, voltage and speed points of the circuit. The calibration information is used to switch the required delays into the circuit path that failed to meet the design specifications.
Careful delay balancing is often constrained severely by physical factors that may make it impossible to achieve such output hold and delay requirements concurrently without resorting to more sophisticated solutions. Custom circuit designs that track process require careful construction and are not available to the ASIC (Applications Specific Integrated Circuit) customer or designer. A limited set of pre-designed sub-circuits are available to an ASIC designer as building blocks. Custom circuits are a luxury for the ASIC designer.
In addition, solutions involving the use of ring oscillators also suffer from the limitation that ring oscillators of the required kind are not available as building blocks from most ASIC manufacturers.